AN726 vishay siliconix faxback 408-970-5600, request 70849 09-dec-98 www.siliconix.com 1 design high frequency, higher power converters with si9166 by kin shum introduction the si9166 is a controller ic designed for dc-to-dc conversion applications with 2.7-v to 6-v input voltage. like its sister device, the si9165, the si9166 provides operation with high operating frequencies, high efficiency, a high level of integration, and low-noise performance. the key difference from the si9165 is that the si9166 uses external mosfets, which gives designers more flexibility in increasing the power level of dc-to-dc conversion circuitry. the si9166 can be easily configured as a synchronous buck or a boost converter with external mosfets operating at switching frequencies as high as 2 mhz, which enables smaller and lighter designs. high efficiency can be preserved at light load by running the converter in pulse skipping modulation (psm) mode. key functions of the si9166 controller are discussed in the description section of the data sheet. in this application note, additional information is provided, including design guidelines for both buck and boost configurations. some test results are also presented. note that the tips provided apply only to designing with the si9166 controller. please review siliconix application notes an715 and an710 for more general design guidelines. ic description the si9166 is a bicmos controller for dc-to-dc conversion applications. a functional block diagram of the ic internal structure is shown in figure 1. figure 1. AN726
AN726 vishay siliconix 09-dec-98 faxback 408-970-5600, request 70849 2 www.siliconix.com start-up/uvlo the internal under voltage lock out (uvlo) circuit keeps most of the ic function blocks off until the supply voltage (v dd ) increases above 2.4 v. a 100-mv hysteresis is built in to the uvlo point, so the controller will be functional until v dd drops below 2.3 v. this helps to eliminate the ic from bouncing between on and off stages. after the ic is turned on, it takes about 4 ms for the por to be ready, the error amp output to charge up, and the output voltage to start ramping up. the output voltage will need an additional 3 to 4 ms to reach regulation, depending on load condition. by-pass mode when using the si9166, the output voltage regulation point can be set within the input voltage range, regardless of whether a buck or boost configuration is being used. for instance, for an input range of 2.7 v to 4.2 v, the output voltage could be set to 3.3 v. for a boost converter, when the input is higher than 3.3 v, the duty cycle of the switch stays at 0%, and the output voltage follows the input voltage by a voltage drop consisting of inductor resistance and mosfet (in pwm mode) or diode (in psm mode) drop. when the input decreases and approaches 3.3 v, the output drops to the regulation point, and the main switch starts to switch at a minimum duty cycle to keep the output regulated at 3.3 v. this duty cycle increases as the input voltage decreases. in some instances, noise can be generated during the transition because there is a minimum controllable duty cycle for any pwm controller. the frequency and amplitude of this transition noise vary depending on the compensation network. the wider the loop bandwidth (bw), the higher the switching frequency and the lower the output ripple. for a buck converter, when input voltage is higher than 3.3 v, it is stepped down to 3.3 v at the output. as the input decreases and approaches 3.3 v, the switching duty cycle increases to the maximum duty cycle, jumping to 100% and making the high-side switch work like a saturated linear regulator. the output voltage will simply follow the input voltage by the saturation voltage until the input drops below the uvlo voltage or until another user-defined control signal disables the converter. the same noise considerations as for a boost converter apply in this case. buck/boost configuration the si9166 can be easily configured to function as a step- down (buck) or a step-up (boost) converter. figures 2 and 3 show the typical application circuit for buck and boost converters, respectively. the list in table 1 shows the key ic connection differences in the two topologies. table 1. buck and boost pin connection comparison design guidelines following are some design guidelines for buck and boost converters. key components required for a complete converter design are mosfets, an inductor, input/output capacitors, and a compensation network. mosfet selection the switching frequency needs to be determined at the beginning of the design. high switching frequencies allow the use of smaller l/c power stage filters without sacrificing current/voltage ripple characteristics or increasing conduction losses. in addition, fast switching cycles help speed up transient response times. high switching frequencies are often associated with high gate charge and crossover switching losses, which can impair converter efficiency. however, conversion efficiency can be optimized by properly setting the switching frequency and careful selection of the power mosfets. the key selection criteria for the mosfets include maximum specifications for on-resistance, drain-source voltage, gate- source, current, and total gate charge q g . while the voltage ratings are fairly straightforward, it is important to carefully balance on-resistance and gate charge. in typical mosfets, the lower the on-resistance, the higher the gate charge. the power loss of a mosfet consists of conduction losses, gate charge losses, and crossover losses. for lower-current application, gate charge losses become a significant factor, so low gate charge mosfets, such as vishay siliconixs little foot family of pwm-optimized devices, are desirable. the si9166 is designed to drive a pair of external p- and n- channel mosfets. the si6801dq is a pwm-optimized low gate charge complementary p-n mosfet pair. it is the perfect choice for current levels of 1.2 a or lower, while the sibling si6803dq is the perfect choice for current levels up to about 1.8 a. name of pin buck boost mode low high v s input output
AN726 vishay siliconix faxback 408-970-5600, request 70849 09-dec-98 www.siliconix.com 3 figure 2. buck configuration figure 3. boost configuration
AN726 vishay siliconix 09-dec-98 faxback 408-970-5600, request 70849 4 www.siliconix.com inductor selection an inductor is the energy storage component in a converter. choosing an inductor means specifying its size, structure, material, inductance, saturation level, dc-resistance (dcr), and core loss. fortunately, there are many inductor vendors that offer wide selections with ample specifications and test data, such as vishay dale, coilcraft, coiltronics, and sumida. the following are some key parameters that users should focus on. in pwm mode, inductance has a direct impact on the ripple current. the peak-to-peak inductor ripple current can be calculated as where f = switching frequency. higher inductance means lower ripple current, lower rms current, lower voltage ripple on both input and output, and higher efficiency, unless the resistive loss of the inductor dominates the overall conduction loss. however, higher inductance also means a bigger inductor size and a slower response to transients. in psm mode, inductance affects inductor peak current, and consequently impacts the load capability and switching frequency. for fixed line and load conditions, higher inductance results in a lower peak current for each pulse, a lower load capability, and a higher switching frequency. the saturation level is another important parameter in choosing inductors. note that the saturation levels specified in data sheets are maximum currents. for a dc-to-dc converter operating in pwm mode, it is the maximum peak inductor current that is relevant, and which can be calculated using these equations: where h = converter efficiency. this peak current varies with inductance tolerance and other errors, and the rated saturation level varies over temperature. so a sufficient design margin is required when choosing current ratings. a high-frequency core material, such as ferrite, should be chosen, since at 2 mhz, the core loss could lead to serious efficiency penalties. the dcr should be kept as low as possible to reduce conduction losses. with a switching frequency (fsw) capability as high as 2 mhz, the si9166 allows use of small surface-mount inductors which are essential for compact cellular phone designs. the recommended inductance at a 2-mhz fsw is 1.5 h, which offers a good balance between size, ripple current, and efficiency. when a lower switching frequency is chosen, higher inductance is required to match the efficiency and ripple performance at 2 mhz. for instance, a 3-h inductor is preferred for a 1-mhz switching frequency. in psm mode, however, the operation is affected by inductance value but not the switching frequency. input/output capacitor selection low-esr (effective series resistance) capacitors are required on both the input and output to minimize voltage ripple. the esr of the output capacitor also changes the loop stability, and it will be discussed later. at a 2-mhz fsw, a 10-f surface-mount ceramic capacitor is recommended at the output of the si9166. a 10-f ceramic or 22-f low-esr tantalum capacitor is recommended as the input filtering capacitor. of course, the voltage rating on capacitor must not be neglected. diode selection to maximize converter efficiency, the use of an external schottky diode is strongly recommended over utilizing the internal body diode of the mosfet, which will typically have a higher forward voltage drop by comparison. the schottky diode must be connected across the synchronous rectifying switch. in pwm mode, it carries the inductor current flow during bbm time; in psm mode, this diode conducts all the time during inductor discharge since the rectifier switch is turned off during psm. a low forward drop diode is preferable for its efficiency advantages and fast recovery times, which help reduce high-frequency noise. compensation network voltage mode control is used in the si9166 for both buck and boost converter configurations. the output voltage is sensed and fed back (pin 10, fb) to be compared with a reference voltage. the difference is amplified by the internal error amplifier. then the output of the error amp (pin 11, comp) is compared with a fixed ramp signal (see figure 1), and the comparator output is a controlled pulse width used to drive the switches. as the switching duty cycle varies, the output voltage is regulated. this single control loop needs to be compensated so that the converter meets following specifications: ? control loop stability margin ? overshoot/undershoot at the output voltage induced by load and line transients ? settling time for overshoot/undershoot for buck, i pp C v out v in v out C () v in lf ------------------------------------------------ - = (1) for boost, i pp C v in v out v in C () v out lf ------------------------------------------- = (2) for buck, i pk i out i pp C 2 ---------- - + = (3) for boost, i pk v out i out h v in -------------------------- i pp C 2 ---------- - + = (4)
AN726 vishay siliconix faxback 408-970-5600, request 70849 09-dec-98 www.siliconix.com 5 figure 4. type i compensation network figure 5. type iii compensation network the peak overshoot/undershoot voltage is determined by closed-loop output impedance (zo). the higher the output impedance, the higher the peak. although heavily dependent on output capacitance and inductance, zo is also closely related to closed loop gain. with fixed power stage components, a control loop with high bandwidth (bw) has low zo. improving the compensation network is more cost- effective than increasing the size of the output capacitor and inductor. fast settling times also rely on good loop design with high bw. adding capacitance at the output of the power supply can reduce the peak deviation, but it can also produce several unintended results, including low bw, long settling times, reduced phase margin, and even system instability. for voltage-mode control, a simple type i compensation network can easily stabilize the loop but at a cost of lower bw, which has to be at least one decade below the l-c corner frequency to preserve a good stability margin. however, type iii compensation, a more complicated design, enables higher bw even above the l-c double-pole. this double pole is straight forward for a buck converter, but more complicated for a boost converter, in which input and output conditions vary. the formula for this double pole is shown in (5). as this double pole shifts to lower frequencies, the phase delay also comes in at a lower frequency, making it difficult to cross over with the same bw. another troublesome feature of boost power stages are their right-half-plane (rhp) zero, which can create difficulties for power supply designers. this rhp zero also varies with operating conditions as shown in (6). when high boost ratios and heavy loads are required, this zero can move to low frequency. the negative effect of this is that it results in gain boost with an extra phase delay that will introduce instability into the loop gain. for both buck and boost converters, the close loop design goal with type iii compensation is to have the final loop gain crossing over after the worst case (lowest) double-pole. to achieve this, two zeroes are required before the double-pole to build up phase boost. the two poles should be placed one decade after the best case (highest) crossover frequency to avoid any phase dragging. the divider resistor pair, r1 and r2 in figure 3 and r2 and r4 in figure 2, determine the output regulation point. since r1 is part of the compensation network, vishay siliconix recommends adjusting r2 to change the regulation voltage without affecting the loop gain. with fixed r1, r2 can be easily calculated by (7) for the desired output voltage setting. the typical value for v ref is 1.3 v. layout issues one of the very few drawbacks of switching power supplies is the noise level induced by their high-frequency switching performance. parasitic inductance and junction capacitance become significant noise sources when a converter is switching at megahertz frequencies. however, noise levels can be minimized by properly laying out the components. here are some tips for laying out buck and boost converters with the si9166 controller. ? minimize power traces. since most power traces, in both buck and boost converters, carry pulsating current, energy stored in trace inductance during the pulse will be released when the pulse current stops, causing high frequency ringing with junction capacitor of the mosfets/diode or even the input/output capacitor. designers will need to keep external power traces as short as possible, including the trace from input/output capacitor to the switch, inductor to f double pole C v in 2 p v out lc ---------------------------------- = (5) f rhp zero C v in 2 2 p v out i out l ------------------------------------- - = (6) r 2 r 1 v out v ref ------------- - 1 C ----------------------- - = (7)
AN726 vishay siliconix 09-dec-98 faxback 408-970-5600, request 70849 6 www.siliconix.com switch, inductor to input/output capacitor, and, of course, the ground trace. ? the decoupling capacitor v dd has to be as close as possible to the pin to reduce the noise on this power source for the internal logic circuit. ? the v s pin has to be close to input or output capacitor for buck or boost converters, respectively, to provide enough gate drive current without sacrificing much driving voltage. if this creates an impossible layout situation, designers may want to consider adding a 1-f ceramic capacitor at the v s pin, depending on the noise level. ? a high-frequency capacitor, normally a 0.1-f ceramic capacitor, is recommended across the sources of the two mosfets-right at the pins if possible-to reduce high- frequency noise. the impedance of these capacitors is lower at high frequencies compared with higher-value capacitors. ? to keep the gate signal clean, they have to be placed away from the inductor, since the alternating magnetic field is the primary noise source in a switching converter. see si9166 buck and boost demo board layout as examples. other issues sometimes higher input capacitance values are required when ultra-high-speed, large-scale load transients occur at a 2.7-v or lower input voltages. if the voltage level at v dd drops below 2.3 v, the uvlo circuit will instantaneously shut off the ic and collapse the output. best results can be achieved when a higher-value r-c filter is used on v dd pin in conjunction with higher input capacitance. the psm feature is designed to increase efficiency under light load conditions and extend battery life. it does not offer an efficiency advantage over pwm mode when the load exceeds 100 ma and a 1.5-h inductor is used. (efficiency data is given in the experimental results section.) however, with a maximum of 1.5-h inductance, the si9166 psm mode guarantees output regulation up to a 150-ma load for both buck and boost converters under any input/output condition. experimental results the si9166 controller has been fully tested in both buck and boost modes on demo boards. some test results are summarized here. typical waveforms for the waveforms shown, the channel lineup from top to bottom is: ? channel 1 - mosfet drain (pin 1 and 8) ? channel 2 - high side switch drive (si9166 pin 3) ? channel 3 - low side switch drive (si9166 pin 14) figure 6. buck db pwm mode: v in = 3.6 v, v o = 2.7 v, load = 200 ma
AN726 vishay siliconix faxback 408-970-5600, request 70849 09-dec-98 www.siliconix.com 7 figure 7. buck db pwm mode: v in = 3 v, v o = 3.6 v, load = 200 ma figure 8. buck db psm mode: v in = 3.6 v, v o = 2.7 v, load = 20 ma figure 9. buck db psm mode: v in = 3.0 v, v o = 3.6 v, load = 20 ma
AN726 vishay siliconix 09-dec-98 faxback 408-970-5600, request 70849 8 www.siliconix.com efficiency figure 10. buck mode efficiency w/ v out = 2.7 v figure 11. bost mode efficiency w/ v out = 3.6 v
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